1. Field of the Invention
The invention concerns a digital operand formatting stage, and more specifically, an optimised CMOS digital operand formatting circuit for controlling the format of digital data presented to the inputs of a full adder.
2. Discussion of the Related Art
FIG. 1 illustrates a block diagram of an embodiment of a known digital operand formatting stage, which in fact is a 4-to-1 multiplexer 10; such a multiplexer 10 has an application within arithmetic logic units (ALU's), where one multiplexer 10 is used to format one digital input operand of an ALU prior to addition.
Referring to FIG. 1, the multiplexer 10 has four data input terminals, 12 to 15 inclusive, four switching input control terminals, 16 to 19 inclusive, and one data output terminal 20.
Terminal 12 carries a data input signal IN that represents a bi-state data input signal, whilst terminal 13 carries the inverse data input signal IN- of the data input signal IN carried on terminal 12. The data input signal IN- of terminal 13 can easily be generated by connecting the respective input and output terminals of an inverter I1 to terminals 12 and 13, respectively, of multiplexer 10, as illustrated.
Terminal 14 carries a fixed logic state data input signal 0. Terminal 15 carries a fixed logic state data input signal 1. Terminals 14 and 15 always have fixed, complimentary, logic state data input signals.
Terminals 16, 17, 18 and 19 carry the respective switching input control signals CS1, CS2, CS3 and CS4 inclusive. Switching control signals CS1 to CS4 inclusive are designed and controlled such that one of the signals present on terminals 12 to 15 inclusive appears on the data output terminal 20.
The data output terminal 20 carries an output data signal OUT that represents one of the four data input signals IN, IN-, 0 or 1 carried by terminals 12, 13, 14 or 15, respectively. The data output signal OUT can have the same logic state of any one of the input data signals i.e. IN, IN- , 0 or 1, depending upon the logic states of the switching input control signals CS1 to CS4 inclusive.
FIG. 2 illustrates a more detailed circuit diagram of an embodiment of multiplexer 10.
Referring to FIG. 2, multiplexer 10 comprises four buffered transmission gates 22, 24, 26 and 28 and an output inverting buffer I2.
Each of the buffered transmission gates 22, 24, 26 and 28 comprises an input inverting buffer, respectively I3, I4, I5 and I6, and a transmission gate, respectively 30, 32, 34 and 36.
The respective input terminals 12, 13, 14 and 15 of inverter I1 and the inverting buffers I2, I3 and I4 carry the respective data input signals IN, IN- , 0 and 1.
Each of the transmission gates 30, 32, 34 and 36 comprise an n-channel transistor MN1, a p-channel transistor MP1 and an inverter I7.
The gate terminals of transistors MN1 and MP1 are respectively connected to the input and output terminals of inverter I7.
The gate terminals of transistors MN1; within the transmission gates 30, 32, 34 and 36, represent the switching input control terminals 16, 17, 18 and 19, respectively.
The respective source terminals of transistors MN1 and MP1; within each of the transmission gates 30, 32, 34 and 36, are connected together and are respectively connected to the output terminals, 38, 40, 42 and 44, of the inverting buffers I3, I4, I5 and I6, respectively.
The respective drain terminals of transistors MN1 and MP1; within the transmission gates 30, 32, 34 and 36, are connected together and are respectively connected to the input terminal 46 of the output inverting buffer I2.
The output terminal 20 of inverting buffer I2 carries the output signal OUT.
Inverters I1 to I7 inclusive, are operatively connected to a positive and negative voltage supply rail, respectively VDD and VSS (not illustrated).
Regarding the operation of the circuit illustrated in FIG. 2; only one of the switching input control signals CS1 to CS4 inclusive, will have a high logic state i.e. logic 1, at any one time, therefore only one of the transmission gates 30, 32, 34 or 36 will be able to pass a signal.
For example, assuming that the switching input control signal CS1 on terminal 16 has a high logic state; input control signals CS2, CS3 and CS4 all have low logic states, only transistor MN1 will pass the signal from the input 38 to the output 46 of transmission gate 30 when the logic state of the signal at the input 38 of the data switch is a logic low i.e. logic 0. However, if the logic state of the signal at the input 38 of transmission gate 30 is a logic high i.e. logic 1, it is transistor MP1 that will pass the signal from the input 38 to the output 46 of transmission gate 30. Therefore, the signal OUT on terminal 20 will have the same logic state as that of signal IN on terminal 12, regardless of its state. The same operational principle applies to transmission gates 32, 34 and 36.
FIG. 2. illustrates only one of several possible embodiments of a circuit that can format a digital operand.
The drawback associated with the circuit of FIG. 2, and other embodiments, is that it requires a considerable number of transistors for its implementation. If FIG. 2 is assumed to be implemented in a CMOS technology and used in conjunction with a 16-bit ALU, then 896 transistors would be required for the formatting of all the input digital operands to the ALU. It is well known that the more transistors there are in a system, the more: space is required; power is consumed; unreliable the system becomes, and the more is the design effort and time that is required.